1. Field of the Invention
The present invention relates to a memory controller and an operating method for the same, especially to a memory controller for using a downgrade memory with initialization step and an operating method for the same
2. Description of Prior Art
FIG. 1 shows a block diagram of a conventional DDR SDRAM, which exemplifies a prevailing DRAM structure since the commencement of SDRAM. The shown memory is divided into a plurality of banks selected by bank address. The memory cells in each bank are accessed through a plurality of column addresses and a plurality of row addresses. As also shown in this figure, the column addresses and the row addresses are generally accessed in multiplexing way as the capacity size of DRAM memory increases. Taking a 256M (32M*8) memory as example, all the address pins A0-A12 in address bus shown on left-top side of FIG. 1 are allocated to row address, while part of the address bus (for example, A0-A9) are allocated to column address in multiplexing fashion to save pin count. As also shown in FIG. 1, the bus of the memory also comprises bank address BA0, BA1 to select memory bank, control signal pins /CAS, /RAS, /WE, and /CS (where slash “/” indicated inverted active signal) and data signal pins DQ0-DQ7. The address pins A0-A12 and BA0, BA1 can also be used for setting mode registers besides addressing.
FIG. 2 shows an allocation table for row address, column address and bank address of a standard SDRAM memory. Taking also the 256M (32M*8) memory as example, the address pin setting for row address, column address and bank address is (2, 13, 10). As can be seen from FIG. 2, the pin counts of the SDRAM memory has specific regulation for correctly accessing the SDRAM memory through a memory controller.
As the progress of semiconductor technology, the capacity of DRAM memory is also rapidly increased. The current operation system also has capability to access memory larger than 4G bytes and the capacity of the commercially available memory is generally larger than 128 M bytes. Semiconductor memories are generally subjected to a test step after manufacture. If the defect of the memory is not serious after examination by the test step, the error can be corrected by redundant memory cells before package of the memory. However, if the defect of the memory is serious, the error cannot be corrected by redundant memory cells. The defected memory will be dropped or used as downgrade memory. In the downgrade memory, only accessible portion in the memory is used and the storage capacity is generally smaller than the normal capacity.
The applications of the conventional downgrade memory have following three ways, or the combination thereof.
As shown in FIG. 3A, in the first conventional way to use downgrade memory, an external redundant memory 76 is used to correct the error of the downgrade memory 70. An external non-volatile memory unit 72 is used to record the defect location and used for the reference of the external redundant memory 76. The external non-volatile memory unit 72 can be realized by, for example, EEPROM or Flash memory and the external redundant memory 76 can be realized by, for example, SRAM or DRAM memory. The external redundant memory 76 can be integrated into ASIC or independently arranged. A comparison/control unit 74 compares an accessing address with defect location and the comparison result is used to control a data bus multiplexer 78 to determine whether the output will be generated by the external redundant memory 76. An alternative way is to use the comparison/control unit 74 to control the DM/DQM signal of memory 70 to control the output from the memory 70 and the external redundant memory 76. The first conventional way has a disadvantage of higher cost caused by the high speed and complicated comparison/control unit 74. The comparison/control unit 74 may need to integrate with the external redundant memory 76 to the same ASIC. However, the use of data bus multiplexer 78 to intercept data bus or the use of DM/DQM signal of memory 70 will cause bus contention problem. The accessing speed of the downgrade memory is limited. Moreover, the use of non-volatile memory unit 72 to record the defect location and the complexity in the comparison/control unit 74 will limit the application of the first conventional way to downgrade memory with less defect.
The second conventional method involves data line division, where the defected areas are precluded in terms of data line DQ. With reference to FIG. 3B, where two 32M*8 SDRAMs are tested and sorted and are used with 32M*1 bit DQ line. For example, if one 32M*8 SDRAM has available area of 32M*2(DQ0-DQ1) and another 32M*8 SDRAM has available area of 32M*6(DQ2-DQ7), the available 2+6=8 DQ lines can be drawn from the two SDRAMs such that a 32M*8 SDRAM is simulated. This method has the advantage of low cost. However, the utilization rate thereof is limited, because the division based on the 32M*1 bit DQ is not compatible with global area layout inside the memory. For example, when all 8 bits for one address are malfunctioned, this defected memory cannot be used as downgrade memory by this method even though this defect is minor.
The third conventional method uses address line division to preclude the defected area in terms of address line. Taking a 32M*8 DRAM as example (as shown in FIG. 2, the pin setting is Bank*Row*Column=2*13*10), the defected area for this DRAM is corresponding to the portion with Row address A12 being High after test. In other word, the defected area will never be accessed if the Row address A12 is kept pulling High. In this situation, as shown in FIG. 3C, the defected area can be precluded by always pulling low the physical address line A12. With reference also to FIG. 2, the memory downgraded in this way can be used as a standard 16M*8 DRAM. This downgrade method has the advantage of versatile variation because the address line has large amount. The variation can also be applied to pull High/Low, address inversion etc. The downgrade method can be performed for one fold downgrade or two fold downgrade (32M*8 down to 8M*8) or more folds. However, the downgrade method has the disadvantage of involving ASIC for address conversion. If the address line to be processed is not an exclusive address line, namely, the address line is multiplexed for row address and column address; ASIC is needed for address conversion. Moreover, the downgraded memory may not be a standard DRAM after address line division. For example, a 16M*8 DRAM (Bank*Row*Column=2*12*10) is downgraded by pulling low the A11 address line, however, this downgraded memory is not a standard DRAM as can be reference to FIG. 2. Therefore, an ASIC is needed to convert the signal of the downgraded memory to simulate an 8M*8 DRAM with pin assignment Bank*Row*Column=2*12*9. Moreover, for advanced DRAM memory such as SDRAM and its successors, the address lines there are also used for initialization commands such as MRS, EMRS commands. Therefore, additional ASIC is needed for signal conversion, which can be referred to Taiwan Patent No. 198183. This patent is also filed by the same applicant as the present invention.
However, the above-mentioned related art has the disadvantages of high cost and signal delay to hinder high-speed application. Moreover, various ASICs are needed for different address conversion schemes, this is inflexible. Moreover, the above-mentioned related art downgrade method is limited to certain conversion, for example, column address reduction instead of column address augmentation.